Thermal-Safe Test Scheduling for Core-Based System-on-a-Chip Integrated Circuits

Overheating has been acknowledged as a major problem during the testing of complex system-on-chip (SOC) integrated circuits. Several power-constrained test scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the non-uniform distribution of heat dissipation across the die and the physical adjacency of simultaneously active cores. This paper proposes a new test scheduling approach that is able to produce short test schedules and guarantee thermal-safety at the same time. Two thermal-safe test scheduling algorithms are proposed. The first algorithm computes an exact (shortest) test schedule that is guaranteed to satisfy a given maximum temperature constraint. The second algorithm is a heuristic intended for complex systems with a large number of embedded cores, for which the exact thermal-safe test scheduling algorithm may not be feasible. Based on a low-complexity test session thermal cost model, this algorithm produces near-optimal length test schedules with significantly less computational effort compared to the optimal algorithm

SystemC-based Minimum Intrusive Fault Injection Technique with Improved Fault Representation

In this paper, we propose a new SystemC-based fault injection technique that has improved fault representation in visible and on-the-fly data and signal registers. The technique is minimum intrusive since it only requires replacing the original data or signal types to fault injection enabler types. We compare the proposed simulation technique with recently reported SystemC-based techniques and show that our technique has fast simulation speed, better fault representation, while maintaining simplicity and minimum intrusion. We demonstrate fault injection capabilities in a behavioural SystemC description of MPEG-2 decoder using proposed technique and show that up to 98.9% fault representation within data and signal registers can be achieved

Cost Model-Driven Test Resource Partitioning for SoCs

The increasing complexity of modern SoCs and quality expectations are making the cost of test represent an significant fraction of the manufacturing cost. The main factors contributing to the cost of test are the required number of tester pins, the test application time, the tester memory requirements and the area overhead required by the test resources. These factors contribute with different weights, depending on the cost model of each product. Several methods have been proposed to optimize each of these factors, however none of them allows an objective function derived from the actual cost model of each product. In this paper, we propose a cost model-driven test resource allocation and scheduling method that minimizes the cost of test

Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems

Recently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the fault-tolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone

Power constrained test scheduling using power profile manipulation

This paper presents a novel power profile manipulation technique which reduces the testing time of the recently proposed power constrained test scheduling algorithms. The power profile manipulation technique consists of reordering and rotating test sequences and a new power approximation model. It is shown when the proposed power profile manipulation is integrated in power conscious test scheduling, savings up to 25% in testing time are achieved using benchmark circuits synthesized in AMS 0.35µm technology

Bridging fault test method with adaptive power management awareness

A key design constraint of circuits used in handheld devices is the power consumption, mainly due to battery life limitations. Adaptive power management (APM) techniques aim to increase the battery life of such devices by adjusting the supply voltage and operating frequency, and thus the power consumption, according to the workload. Testing for resistive bridging defects in APM-enabled designs raises a number of challenges due to their complex analog behavior. Testing at more than one supply voltage setting can be employed to improve defect coverage in such systems, however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes a multi-Vdd automatic test generation method which delivers 100% resistive bridging defect coverage and also a way of reducing the number of supply voltage settings required during test through test point insertion. The proposed techniques have been experimentally validated using a number of benchmark circuits

Genomic correlates of glatiramer acetate adverse cardiovascular effects lead to a novel locus mediating coronary risk

Glatiramer acetate is used therapeutically in multiple sclerosis but also known for adverse effects including elevated coronary artery disease (CAD) risk. The mechanisms underlying the cardiovascular side effects of the medication are unclear. Here, we made use of the chromosomal variation in the genes that are known to be affected by glatiramer treatment. Focusing on genes and gene products reported by drug-gene interaction database to interact with glatiramer acetate we explored a large meta-analysis on CAD genome-wide association studies aiming firstly, to investigate whether variants in these genes also affect cardiovascular risk and secondly, to identify new CAD risk genes. We traced association signals in a 200-kb region around genomic positions of genes interacting with glatiramer in up to 60 801 CAD cases and 123 504 controls. We validated the identified association in additional 21 934 CAD cases and 76 087 controls. We identified three new CAD risk alleles within the TGFB1 region on chromosome 19 that independently affect CAD risk. The lead SNP rs12459996 was genome-wide significantly associated with CAD in the extended meta-analysis (odds ratio 1.09, p = 1.58×10-12). The other two SNPs at the locus were not in linkage disequilibrium with the lead SNP and by a conditional analysis showed p-values of 4.05 × 10-10 and 2.21 × 10-6. Thus, studying genes reported to interact with glatiramer acetate we identified genetic variants that concordantly with the drug increase the risk of CAD. Of these, TGFB1 displayed signal for association. Indeed, the gene has been associated with CAD previously in both in vivo and in vitro studies. Here we establish genome-wide significant association with CAD in large human samples.This work was supported by grants from the Fondation Leducq (CADgenomics: Understanding CAD Genes, 12CVD02), the German Federal Ministry of Education and Research (BMBF) within the framework of the e:Med research and funding concept (e:AtheroSysMed, grant 01ZX1313A-2014 and SysInflame, grant 01ZX1306A), and the European Union Seventh Framework Programme FP7/2007-2013 under grant agreement no HEALTH-F2-2013-601456 (CVgenes-at-target). Further grants were received from the DFG as part of the Sonderforschungsbereich CRC 1123 (B2). T.K. was supported by a DZHK Rotation Grant. I.B. was supported by the Deutsche Forschungsgemeinschaft (DFG) cluster of excellence ‘Inflammation at Interfaces’. F.W.A. is supported by a Dekker scholarship-Junior Staff Member 2014T001 - Netherlands Heart Foundation and UCL Hospitals NIHR Biomedical Research Centre

New genetic loci link adipose and insulin biology to body fat distribution.

Body fat distribution is a heritable trait and a well-established predictor of adverse metabolic outcomes, independent of overall adiposity. To increase our understanding of the genetic basis of body fat distribution and its molecular links to cardiometabolic traits, here we conduct genome-wide association meta-analyses of traits related to waist and hip circumferences in up to 224,459 individuals. We identify 49 loci (33 new) associated with waist-to-hip ratio adjusted for body mass index (BMI), and an additional 19 loci newly associated with related waist and hip circumference measures (P < 5 × 10(-8)). In total, 20 of the 49 waist-to-hip ratio adjusted for BMI loci show significant sexual dimorphism, 19 of which display a stronger effect in women. The identified loci were enriched for genes expressed in adipose tissue and for putative regulatory elements in adipocytes. Pathway analyses implicated adipogenesis, angiogenesis, transcriptional regulation and insulin resistance as processes affecting fat distribution, providing insight into potential pathophysiological mechanisms